Integrated circuits may be formed using various photolithographic techniques. Such techniques typically involve exposing a photoresist layer to a light source through a patterned photo-mask. In general, the final pattern formed onto the photoresist layer does not precisely match the designed pattern for which the final pattern was formed. This is caused by various photolithographic process parameters such as the resolution of the light source. It is important to ensure that the final printed pattern is not so far from the designed pattern that functionality of the circuit is adversely affected.
In many cases, the entity that designs a circuit is different from the entity that manufactures the circuit. Because the manufacturing processes, such as the photolithographic processes include parameters that are specific to a particular integrated circuit manufacturer, the manufacturer must analyze each layer of the design separately to ensure that a particular layer does not include circuit features that may cause an issue with the manufacturers photolithographic processes. Various tools exist to perform this check. An example of such a tool is Litho Process Check (LPC) by Cadence Design Systems, Inc. These tools, however, analyze each layer separately and do not factor in effects from other layers
Additionally, the circuit designing entity often uses various tools to find critical paths through the circuit. One example of such a tool is On-Chip Critical Path. Such tools allow the circuit designer to determine things like critical paths through the circuit and assist the designer with time delay, cost reduction, trouble shooting, and other issues. Such tools will analyze multiple layers together. However, such tools do not factor in any manufacturer specific photolithographic process parameters. Consequently, it is desired to have a tool that will allow circuit designers or manufacturers to consider both critical path issues from multiple layers as well as manufacturer specific photolithographic process parameters.